1. Field
Example embodiments relate to a semiconductor integrated circuit. More particularly, example embodiments relate to an electric charge transfer switch circuit for selectively controlling a body bias voltage of a charge transfer device and a boosted voltage generating circuit having the same.
2. Description of the Related Art
Recently, DRAMs have been developed that are directed towards increasing the integration degree of memory cells of DRAMS while reducing the size of each memory cell and lowering an external supply voltage for the DRAM. For example, a supply voltage VDD for a DRAM may be lowered from approximately 5V to approximately 1.8V or 1.5V. If the supply voltage VDD is lowered to approximately 1.5V, a boosted voltage generating circuit may be used and/or required in a conventional DRAM to generate a boosted voltage of approximately 3.0 V or more. The boosted voltage may be applied to a word line, a bit line, and a sense amplifier of a conventional DRAM. If a sense amplifier of a DRAM operates with a low external supply voltage, the operating speed of the sense amplifier is generally reduced and thus, the sense amplifier should generally operate with a boosted voltage. Also, in order to perform precharging of a bit line and a high speed write operation of a memory cell, a gate voltage for controlling the operations of transistors should be boosted.
FIG. 1 is a conceptual diagram illustrating a conventional boosted voltage generating circuit 100. Referring to FIG. 1, the boosted voltage generating circuit 100 includes three-stage pumping circuits 110, 120, and 130. The pumping circuits 110 through 130 sequentially perform pumping operations to generate a boosted voltage VPP. The pumping circuits 110 through 130 include capacitors C110, C120, C122, and C130 and switches S110, S120, S122, S124, S126, S130, S132, and S134, and boost nodes N110, N120, N122, and N132 to boost a voltage VPP to a voltage that is two or three times higher than a supply voltage VDD.
In the conventional boosted voltage generating circuit 100, the first pumping circuit 110 precharges the first boost node N110 to the supply voltage VDD in response to a first pumping signal P1, and boosts the first boost node N110 in response to a second pumping signal P2. The second pumping circuit 120 precharges the second and third boost nodes N120 and N122 in response to the first pumping signal P1, and boosts the second and third boost nodes N120 and N122 in response to the second pumping signal P2 and a third pumping signal P3, respectively. The third pumping circuit 130 precharges the fourth boost node N132 to the supply voltage VDD in response to the first pumping signal P1, and boosts the fourth boost node N132 in response to a fourth pumping signal P4.
In FIG. 1, the first pumping signal P1 controls the switches S110, S120, S122, and S130, and boosts the voltages of the first to fourth boost nodes N110, N120, N122, and N132 to the supply voltage VDD. The second pumping signal P2 is used to increase charges at the first and second boost nodes N110 and N120 via the capacitors C110 and C120, respectively. The third pumping signal P3 is used to increase charge at the third boost node N122 via the capacitor C122, and the fourth pumping signal P4 is used to increase charge at the fourth boost node N132 via the capacitor C130.
As shown in FIG. 1, the second boost node N120 is connected to the third boost node N122 to further increase the charge at the third boost node N122 via the switch S124. Likewise, the first and third boost nodes N110 and N122 are connected to the fourth boost node N132 to further increase charge at the fourth boost node N132 via the switches S126 and S132, respectively. The charge at the fourth boost node N132 is generated as the boosted voltage VPP via the switch S134. The first through fourth boost nodes N110, N120, N122, and N132 are precharged to the supply voltage VDD via the switches S110, S120, S122, and S130, respectively.
The operation of the conventional boosted voltage generating circuit 100 illustrated in FIG. 1 is described below with reference to a timing diagram illustrated in FIG. 2. Referring to FIG. 2, precharging and pumping operations are performed during a low cycle duration of a row cycle time (tRC) of a conventional memory device. In FIG. 2, a precharging duration is defined to be a duration between times t1 and t2, a first pumping duration is defined to be a duration between times t2 and t3, a second pumping duration is defined to be a duration between times t3 and t4, and a third pumping duration is defined to be a duration between times t4 and t5.
During the precharging duration, the first through fourth boost nodes N110, N120, N122, and N132 are precharged to the supply voltage VDD via the switches S110,S120, S22, and S132 in response to the first pumping signal P1. During the first pumping duration, pumping is performed by the capacitors C110 and C120 in response to the second pumping signal P2. During the second pumping duration, pumping is performed by the capacitor C122 in response to the third pumping signal P3. During the third pumping duration, pumping is performed by the capacitor C130 in response to the fourth pumping signal P4.
In the boosted voltage generating circuit 100 shown in FIG. 1, each of the switches S124, S126, S132, and S134 may be embodied as an NMOS transistor and may function as a charge transfer device. In general, a ground voltage is applied to a body of each of the NMOS transistors, and thus, the NMOS transistors operate while being affected by a negative back bias voltage. Therefore, during charge transfer, a threshold voltage Vt of each NMOS transistor is increased due to the body bias effect. The charge transfer operation of the switch S124, for example, is described with reference to FIG. 3.
It is assumed in FIG. 3 that a ratio of the capacity of the capacitor C120 to that of the capacitor C122 is 1:1. A drain voltage of the NMOS transistor acting as the switch 124 is changed from VDD to 2VDD and then to 1.5VDD when precharging, pumping, and charge transfer are sequentially performed as described with reference to FIG. 2. As a gate voltage of the NMOS transistor is changed from VDD to VDD+VPP, a source voltage of the NMOS transistor is increased from VDD to 1.5 VDD. In this case, a back bias voltage VBS of the NMOS transistor is reduced from −VDD to −1.5VDD and thus, the threshold voltage Vt of the NMOS transistor increased, thereby lowering the efficiency of charge transfer.
Further, if VPP is low, the gate voltage of the NMOS transistor is lowered, thereby significantly reducing the efficiency of charge transfer. Accordingly, VPP should be or is required to be a relatively high voltage.
FIG. 4 illustrates the conventional precharging operation of the switch S124 of FIG. 1. Referring to FIG. 4, a drain voltage of the NMOS transistor acting as the switch S124 is changed from 0.5VDD to VDD after a pumping operation. During a precharging operation, an applied gate voltage of the NMOS transistor is equal to VDD, and when a pumping operation starts in the next stage, a source voltage of the NMOS transistor is increased from 1.5VDD to 2.5VDD. Accordingly, in the beginning of precharging, charges flow backward from a drain of the NMOS transistor to a source thereof.